1. Field Of The Invention
This invention relates to electrical converters and more particularly to an improved low power analog to digital converter.
2. Background Of The Invention
The process of converting an analog signal to a digital signal has been well known to the prior art for a number of years. In general, a process of converting an analog signal into a digital signal comprises measuring the amplitude of the analog signal at consistent time intervals and producing a set of signals representing the measured digital value. The information in the digital signals and the known time interval enables one to convert the digital signal back to the analog signal.
The prior art has known many types of apparatus circuits and the like for accomplishing the process of an analog to digital conversion of an electrical signal. In a typical analog to digital converter, the amplitude of an analog signal is compared to a standard signal during predetermined durations of time known as a sampling period. One specific type of analog to digital converter is commonly referred to as a two-stage flash, pipelined analog to digital converter.
U.S. Pat. No. 4,353,059 to Vaitkus discloses a multithreshold A/D converter having primary and secondary quantizing stages. The threshold reference voltages for the secondary quantizing stages are obtained by amplifying a threshold reference voltage step derived from the primary quantizing stage. Since the secondary threshold reference voltages are derived directly from the primary reference voltages the secondary reference voltages will track deviations occurring within the primary quantizing stage. A reference tracking amplifier is utilized to amplify a portion of the primary reference voltage and apply same to the secondary stage. By using monolithic integrated circuit fabrication techniques to identically match the reference tracking amplifier with the error amplifiers of the primary quantizing stages, the secondary threshold reference voltages will also track deviations in the peak error signals conveyed from the primary to the secondary quantizing stages.
U.S. Pat. No. 5,182,560 to Shiwaku discloses a high speed, low power parallel analog-to-digital converter (100) with comparator (Cj) having sense amplifiers operating with low power, high speed and a ROM encoder (130) also operating in a low power, high speed regime.
U.S. Pat. No. 5,296,858 to Moyal discloses an apparatus for generating a digital signal representing an analog signal comprising a reference array establishing reference values at hierarchically arranged reference nodes in response to a reference signal. The apparatus includes a first iteration comparing circuit comparing selected first reference values present at first nodes with the analog signal. The first reference values establish a plurality of ranges of reference values. The first comparing circuit generates a first output signal indicating a particular range in which the analog signal first compares with respect to a reference value in a predetermined relation. A logic circuit generates a control signal in response to the first output signal. A second comparing circuit effects second comparing of selected second reference values with the analog signal. The second reference values are present at selected nodes which are in the intervals adjacent the first reference nodes and hierarchically segment those intervals. The second comparing circuit responds to the control signal to effect the second comparing and comprises a plurality of second comparators. Each second comparator receives the analog signal as a first input and receives hierarchically equal of the second reference values from the intervals as a plurality of available second inputs. One of the available second inputs is selected as the second input value to each second comparator in response to the control signal. The second comparing circuit generates a second output and the logic means responds to the first output and the second output to generate the digital signal output.
U.S. Pat. No. 5,450,085 to Stewart et al. discloses an analog to digital conversion of signals at rates higher than can be accomplished by a monolithic flash analog to digital converter is achieved using multiple flash analog to digital converters operated in a parallel architecture. Sample timing of the multiple converters is skewed by selecting subfrequencies of a control clock or different phases of a control clock as the source for the sample control signal. The multiple flash converter outputs are then digitally recombined to produce after operating at single output identical to a flash converter operating at a higher speed than could be obtained for a given set of circuit parameters.
U.S. Pat. No. 5,491,435 to Mun et al. discloses a data sensing circuit for a semiconductor memory device having complementary bit lines, including a PMOS sense amplifier connected between the complementary bit lines, an NMOS sense amplifier connected between the complementary bit lines, a bit line equalization and precharge circuit connected between sensing control nodes of the PMOS and NMOS sense amplifiers, a plurality of first capacitors, a plurality of second capacitors, a plurality of first fuses connected between the sensing control node of the PMOS sense amplifier and respective ones of the first capacitors, a plurality of second fuses connected between the sensing control node of the NMOS sense amplifier and respective once of the second capacitors. Selected ones of the first and/or second fuses can be selectively blown thereby couple selected ones of the first and/or second cap capacitors to the sensing control nodes of the of PMOS. and NMOS sense amplifiers, respectively, to thereby equalize the capacitances of the sensing control nodes even when they have different parasitic capacitances.
U.S. Pat. No. 5,751,170 to Pytheon discloses a circuit for a low voltage sense amplifier obtains a faster time in designing a circuit because a conventional sense amplifier adopting voltage 3.33V can be applied to a semi-conductor memory device requiring a potential of less than 1.0V, and prevents current leakage at a low threshold voltage by providing source voltage to a sense amplifier of a selected memory cell array in an active mode as well as in a standby mode.
Therefore, it is an object of the present invention to provide an improved analog to digital converter that overcomes the deficiencies of the analog to digital converters of the prior art-and provides a significant advancement to the electrical conversion art.
Another object of this invention is to provide an improved analog to digital converter that operates without the use of DC circuits for reducing operating power.
Another object of this invention is to provide an improved analog to digital converter that operates on a very low power level in the order of 50 xcexcW/M Hz-bit.
Another object of this invention is to provide an improved analog to digital converter incorporating an eight bit two stage pipeline flash converter instead of serial or parallel processing.
Another object of this invention is to provide an improved analog to digital converter that is capable of operating up to 100 Mhz.
Another object of this invention is to provide an improved analog to digital converter capable of extendability in excess of ten bits of resolution.
Another object of this invention is to provide an improved analog to digital converter that is a semiconductor process scalable from 0.5 xcexcM to 0.1 xcexcM.
Another object of this invention is to provide an improved analog to digital converter incorporating an automatic calibration for compensating for variations incurred during the manufacturing processes.
Another object of this invention is to provide an improved analog to digital converter incorporating a test and calibration for compensating for variations incurred during operation of the improved making analog to digital converter.
Another object of this invention is to provide an improved analog to digital converter that is compatible for incorporating within large-scale integrated circuits.
The foregoing has outlined some of the more pertinent objects of the present invention. These objects should be construed as being merely illustrative of some of the more prominent features and applications of the invention. Many other beneficial results can be obtained by applying the disclosed invention in a different manner or modifying the invention with in the scope of the invention. Accordingly, other objects in a full understanding of the invention may be had by referring to the summary of the invention and the detailed description describing the preferred embodiment of the invention.
The present invention is defined by the appended claims with specific embodiments being shown in the attached drawings. For the purpose of summarizing the invention, the invention relates to an improved analog to digital converter for converting an analog signal into a digital signal comprising an input circuit and a reference circuit for generating a series of reference signals. A first converter is connected to the input circuit and the reference circuit for comparing the input signal to the reference signals for determining the most significant digital value of the input signal. A second converter is connected to the input circuit and the reference circuit and the first converter for comparing the input signal to the reference signals for determining the least significant digital value of the input signal.
In a more specific example of the invention, the input circuit includes a sample and hold circuit for storing the input signal. Preferably, the input circuit includes a sample and hold circuit for storing the input signal during the period the first converter is determining the most significant digital value of the input signal. The sample and hold circuit stores the input signal during the period the second converter is determining the least significant digital values of the input signal.
In another example of the invention, the reference circuit includes a voltage divider for generating a series of reference signals. The first converter comprises a flash converter for determining the most significant digital values of the input signal using the full range of reference signal. The second converter comprises a flash converter for determining the least significant digital values of the input signal using a selected range of the input signal. The first converter determines only the most significant digital values of the input signal. The second converter determines only the least significant digital values of the input signal. The first converter determines only the most significant digital value of the input signal. The second converter determines only the least significant digital value for the most significant digital value determined by the first converter. A multiplicity of the least significant digital values being equal to one of the most significant digital values.
The invention relates to an improved comparator circuit for comparing an input signal with a reference signal comprising a first comparator stage connected to the input signal and the reference signal for providing a first amplification at a lower gain and at an initial slower rate of comparison. A second comparator stage provides a second amplification at a higher gain and at a higher rate of comparison. A latch circuit receives an output of the second comparator stage for holding an out representative of the comparison of the input signal with a reference signal.
The invention relates to an improved compensation circuit for improving the accuracy of an operating circuit comprising an array of capacitors for generating a variable binary internal signal to provide a wide range of compensation for the operating circuit. An array of switches interconnect the array of capacitors to an array of memories. The array of switches interconnect selective capacitors of the array of capacitors to selected memories of the array of memories for improving the accuracy of an operating circuit.
The foregoing has outlined rather broadly the more pertinent and important features of the present invention in order that the detailed description that follows may be better understood so that the present contribution to the art can be more fully appreciated. Additional features of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and the specific embodiments disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.